?2000 imp, inc. 408-432-9100/www.impweb.com 1 imp5226 imp5226 d ata c ommunications key features ultra-fast response for fast-20 scsi 35mhz channel bandwidth sleep-mode current less than 150? ?disconnects terminator from lows no external compensation capacitors compatible with active negation drivers compatible with passive and active terminations approved for use with scsi 1, 2, 3 and ultra scsi hot-swap compatible pin-for-pin compatible with lx5226, lx5207 and ucc5610 block diagrams + current biasing circuit thermal limiting circuit 24ma current limiting circuit term power data output pin db (0) 1 of 18 channels disconnect v term 1.4v 2.85v 5226_01.eps 1 1 8-line plug and pla 8-line plug and pla y y scsi t scsi t er er minat minat or or the 18-channel imp5226 scsi terminator is part of imp's family of high- performance scsi terminators that deliver true ultrascsi performance. the bicmos design offers superior performance over first generation linear regulator/resistor based terminators. imp's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35mhz, which is 100 times faster than the older linear regulator termi- nator approach. the bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500khz since a large output stabilization capacitor is required. the imp architecture eliminates the external output compensation capacitor and the need for transient output capacitors while maintaining pin compatibility with first generation designs. reduced component count is inherent with the imp5226. the imp5226 architecture tolerates marginal system designs. a key improvement offered by the imp5226 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to rec- ommended scsi hardware design guidelines, such as improper cable lengths and impedance. frequently, this situation is not controlled by the peripheral or host designer. the imp5226 can be placed in a sleep mode with a high logic signal. in the sleep mode the outputs are in a high impedance state. quiescent cur- rent is less than 150 a when disabled. the imp5226 is a superior pin-for-pin replacement for the lx5226, lx5207, uc5601/5602 and the ucc5610. t r a ps l e n n a h ce p y t 1 1 1 5 p m i9e s 2 1 1 5 p m i9e s 5 1 1 5 p m i9e s 1 2 1 5 p m i7 2e s 8 1 2 5 p m i9e s 9 1 2 5 p m i9e s 5 2 2 5 p m i8 1e s 6 2 2 5 p m i8 1e s 1 4 2 5 p m i8d v l / e s 2 4 2 5 p m i8d v l / e s s p e . 6 0 t _ 6 2 2 5 imp scsi terminators
imp5226 imp5226 2 408-432-9100/www.impweb.com ?2000 imp, inc. pin configuration ordering information absolute maximum ratings 1 10 t6 9 heat sink / gnd 8 gnd 7 heat sink / gnd 6 t5 5 t4 4 t3 3 t2 2 t1 1 disconnect 14 v term 13 t9 12 t8 11 t7 19 t13 20 heat sink / gnd 21 heat sink / gnd 22 heat sink / gnd dwp package 23 t14 24 t15 25 t16 26 t17 27 t18 28 gnd 15 nc 16 t10 17 t11 18 t12 5226_02a.eps imp5226 sowb-28 10 t6 9 heat sink / gnd 8 gnd 7 heat sink / gnd 6 t5 5 t4 4 t3 3 t2 2 t1 1 disconnect 14 v term 13 t9 12 t8 11 t7 19 t13 20 heat sink / gnd 21 heat sink / gnd 22 heat sink / gnd db package 23 t14 24 t15 25 t16 26 t17 27 t18 28 gnd 15 nc 16 t10 17 t11 18 t12 5226_02b.eps imp5226 ssop-28 r e b m u n t r a pe g n a r e r u t a r e p m e te g a k c a p p w d c 6 2 2 5 p m i0 0 7 o t c cb w o s c i t s a l p n i p - 8 2 t p w d c 6 2 2 5 p m i0 0 7 o t c cb w o s c i t s a l p n i p - 8 2 , l e e r d n a e p a t b d c 6 2 2 5 p m i0 0 7 o t c cp o s s c i t s a l p n i p - 8 2 t b d c 6 2 2 5 p m i0 0 7 o t c cp o s s c i t s a l p n i p - 8 2 , l e e r d n a e p a t 3 t a . 1 0 t _ 6 2 2 5 thermal data termpwr voltage . . . . . . . . . . . . . . . . . . . . . . . . +7v signal line voltage . . . . . . . . . . . . . . . . . . . . . 0v to +7v operating junction temperature . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . . . ?5 c to 150 c lead temperature (soldering, 10 sec.) . . . . . . 300 c note: 1. exceeding these ratings could cause damage to the device. all voltages are with respect to ground. currents are positive into, negative out of the specified terminal. dwp package thermal resistance junction-to-leads, jl . . . . . . . . 18 c/w thermal resistance junction-to-ambient, ja . . . . . . 40 c/w db package thermal resistance junction-to-ambient, ja . . . . . . 117 c/w junction temperature calculation: t j = t a + (p d x ja ). the ja numbers are guidelines for the thermal performance of the device/pc-board system. all of the ambient airflow is assumed.
imp5226 imp5226 ?2000 imp, inc. data communications 3 recommended operating conditions r e t e m a r a pl o b m y sn i mp y tx a ms t i n u e g a t l o v r w p m r e tv m r e t 0 . 45 . 5v e g a t l o v e n i l l a n g i s 00 . 5v e g a t l o v t u p n i t c e n n o c s i d 0v m r e t v c 6 2 2 5 p m i e g n a r e r u t a r e p m e t n o i t c n u j g n i t a r e p o 05 2 1c . l a n o i t c n u f s i e c i v e d e h t h c i h w r e v o e g n a r e h t e t a c i d n i s n o i t i d n o c g n i t a r e p o d e d n e m m o c e r . 2 : e t o n s p e . 2 0 t _ 6 2 2 5 electrical characteristics unless otherwise specified, these specifications apply at an ambient operating temperature of t a = 25 c. termpwr = 4.75v. low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature. r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u e g a t l o v h g i h t u p t u ov t u o 5 6 . 25 8 . 2v t n e r r u c y l p p u s r w p m r e ti c c n e p o = s e n i l a t a d l l a0 15 1a m v 2 . 0 = s e n i l a t a d l l a4 2 40 5 4 v 0 . 2 > s n i p t c e n n o c s i d0 50 5 1a t n e r r u c t u p t u oi t u o v t u o v 5 . 0 =0 2 2 2 4 2 a m t n e r r u c t u p n i t c e n n o c s i di n i v 0 = s n i p t c e n n o c s i d0 1 a t n e r r u c e g a k a e l t u p t u oi l o v , v 0 . 2 > s n i p t c e n n o c s i d o v 2 . 0 =1a h t d i w d n a b l e n n a h cw b5 3z h m l e n n a h c r e p , t n e r r u c k n i s n o i t a n i m r e ti k n i s v t u o v 4 =7a m s p e . 3 0 t _ 6 2 2 5
imp5226 imp5226 4 408-432-9100/www.impweb.com ?2000 imp, inc. application information figure 3. 5226_03.eps disconnect 1 meter, awg 28 imp5226 disconnect receiver driver imp5226 figure 1. receiving waveform ?20mhz figure 2. driving waveform ?20mhz
imp5226 imp5226 ?2000 imp, inc. data communications 5 cable transmission theory suggests to optimize signal speed and quality, the termination should act both as an ideal voltage refer- ence when the line is released (deasserted) and as an ideal current source when the line is active (asserted). common active terminators which consist of linear regulators in series with resis- tors (typically 110 ? ) are a compromise. with coventional linear terminators as the line voltage increases the amount of current decreases linearly by the equation; the imp5226, with its unique new architecture, applies the max- imum amount of current regardless of line voltage until the termination high threshold (2.85v) is reached. acting as a near ideal line terminator, the imp5226 closely repro- duces the optimum case when the device is enabled. to enable the device the disconnect pin is pulled low. during this mode of operation, quiescent current is 10ma, and the device will respond to line demands by delivering 24ma on assertion and by imposing 2.85v on deassertion. in order to disable the device, the disconnect pin must be driven high in the disable mode, the device is in a sleep state with quiescent current less than 150 a. when disabled, all outputs are in a high impedance state. sleep mode can be used for power conservation or to remove the terminator from the scsi chain. an additional feature of the imp5226 is its compatibility with active negation drivers. vv r i ref line ? () = . table 1. power up/ power down function table application information t c e n n o c s i ds t u p t u o t n e c s e i u q m u m i x a m t n e r r u c ld e l b a n ea m 5 1 hz i ha 0 5 1 n e p oz i ha 0 5 1 s p e . 4 0 t _ 6 2 2 5
imp, inc. corporate headquarters 2830 n. first street san jose, ca 95134-2071 tel: 408-432-9100 tel: 800-438-3722 fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com the imp logo is a registered trademark of imp, inc. all other company and product names are trademarks of their respective owners. ? 2000 imp, inc. printed in usa publication #: 7009 revision: c issue date: 07/31/00 type: preliminary imp5226 imp5226 s e h c n is r e t e m i l l i m n i mx a mn i mx a m * ) n i p - 8 2 ( b w o s a8 9 6 . 03 1 7 . 00 7 . 7 10 1 . 8 1 b1 9 2 . 09 9 2 . 00 4 . 70 6 . 7 c3 9 0 . 04 0 1 . 05 3 . 25 6 . 2 d3 1 0 . 08 1 0 . 03 3 . 01 5 . 0 f6 1 0 . 00 5 0 . 00 4 . 07 2 . 1 gc s b 0 5 0 . 0c s b 7 2 . 1 j9 0 0 . 03 1 0 . 03 2 . 02 3 . 0 k4 0 0 . 02 1 0 . 00 1 . 00 3 . 0 m 0 8 0 8 p4 9 3 . 09 1 4 . 00 0 . 0 15 6 . 0 1 ) n i p - 8 2 ( p o s s a8 6 0 . 08 7 0 . 03 7 . 19 9 . 1 b9 0 0 . 05 1 0 . 05 2 . 08 3 . 0 c5 0 0 . 08 0 0 . 03 1 . 02 2 . 0 d6 9 3 . 07 0 4 . 07 0 . 0 13 3 . 0 1 f5 0 2 . 02 1 2 . 00 2 . 58 3 . 5 gc s b 5 2 . 0c s b 5 6 . 0 j2 0 0 . 08 0 0 . 05 0 . 01 2 . 0 k4 6 0 . 02 7 0 . 03 6 . 13 8 . 1 l5 2 0 . 07 3 0 . 05 6 . 05 9 . 0 m 0 8 0 8 p1 0 3 . 01 1 3 . 05 6 . 70 9 . 7 e a 3 1 0 - o m g n i w a r d c e d e j * 3 t a . 5 0 t _ 6 2 2 5 a b p d g f 28 15 14 1 c k j l m seating plane 28-pin (sowb)dwp.eps package dimensions sowb (28-pin) p 28-pin (ssop)db.eps ssop (28-pin)
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